1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method, and more particularly, to a semiconductor device manufacturing method in which a metal silicide layer is formed via an in-situ process, resulting in a simplified overall manufacturing process.
2. Discussion of the Related Art
With the reduction in the geometrical size of semiconductor devices, the areas of gate and source/drain regions are decreasing. Along with this reduction in size, there is a need to reduce the bonding thickness of source/drain regions and the resulting high-resistance regions. To substantially lower resistance in the source/drain regions metal silicides are used for the electrical contacts between those regions, and adjacent polysilicon regions. Such silicides, which may be of platinum, manganese, cobalt, or titanium, are formed wherever the source/drain regions are to come into contact with exposed polysilicon regions by depositing and then heating a thin metal layer having a high fusion point. Such a method for forming a metal silicide layer according to a related art is shown in FIGS. 1A-1F.
Referring to FIG. 1A, a semiconductor substrate 21 is divided into an active region and a device separating region, and a device isolation layer 22 is formed on the semiconductor substrate 21 at the device separating region by use of a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) process. Next, the semiconductor substrate 21 is thermally oxidized at a high-temperature so that a gate oxide layer 23 is formed on the semiconductor substrate 21.
Referring to FIG. 1B, a poly-silicon layer is deposited on the gate oxide layer 23, and is selectively etched via a photo-etching process to form a gate electrode 24. Then, low-density impurity ions are implanted into a surface of the semiconductor substrate 21 at opposite sides of the gate electrode 24 to form a lightly doped drain (LDD) region 25.
Referring to FIG. 1C, an insulation layer is deposited on the surface of the semiconductor substrate 21. Subsequently, the insulation layer is subjected to an etch-back process so that an insulation sidewall 26 is formed at either lateral surface of the gate electrode 24. Then, high-density impurity ions are implanted into the surface of the semiconductor substrate 21 to form a source/drain impurity region 27 by using the gate electrode 24 and the insulation sidewall 26 as a mask.
Referring to FIG. 1D, the semiconductor substrate 21 is subjected to a washing process for removing various objects, such as metal impurities, organic pollutants, natural oxides, etc. Conventionally, the washing process is a chemical washing process using a standard cleaning 1 (SC1) solution and hydrofluoric (HF) or dilute hydrofluoric (DHF) solution. Here, the SC1 solution is an organic matter having a mixing ratio of NH4OH:H2O2:H2O of 1:4:20.
After completing the washing process, the semiconductor substrate 21 is transferred into a sputtering chamber (not shown) of a sputtering apparatus so that a metal layer 28, such as a nickel layer, is formed on the surface of the semiconductor substrate 21 via a sputtering process.
Referring to FIG. 1E, the semiconductor substrate 21 is heat treated at a temperature of 400° C. to 600° C. in a specific apparatus, for example, a rapid thermal process apparatus or an electric furnace. As a result, a metal silicide layer 29 is formed on the surface of the semiconductor substrate 21 at positions corresponding to the gate electrode 24 and the source/drain impurity region 27. The metal silicide layer 29 is obtained as metal ions of the metal layer 28 react with silicon ions of the semiconductor substrate 21 and gate electrode 24 during the heat treatment. The metal layer 28 remains on the insulation sidewall 26 and device isolation layer 22 without reacting.
Referring to FIG. 1F, after removing the non-reacted metal layer 28, which is not used to form the metal silicide layer 29, the semiconductor substrate 21 is subjected to an annealing process at a predetermined temperature. This annealing process stabilizes the phase of the metal silicide layer 29, thereby achieving the low-resistance metal silicide layer 29.
According to the method for forming a metal silicide layer as described above, however, it is necessary to transfer the semiconductor substrate with the deposited metal layer to the specific heating apparatus for the heat treatment necessary to form the metal suicide layer. Such additional heat treatment makes the overall manufacture more complex, it requires an additional apparatus, and it increases the cycling time of the lot in progress.